A background calibration in pipelined ADCs

Authors: Hamid R. Mafi, Amir M. Sodagar

Abstract:
In this paper, a novel background calibration is presented. The proposed scheme continuously measures and digitally compensates conversion errors caused by residue amplifier nonlinearity. This scheme can be used to relax analog circuit requirements for high-precision residue amplifier, accordingly decreasing the power consumption and/or increasing sampling rates in pipelined ADCs. The proposed scheme employs a fifth-order polynomial to eliminate conversion errors. One unique feature of the proposed scheme is that a single pseudorandom sequence, pn, is exploited. The simulation results show that, using the proposed calibration technique, the signal-to-noise-and-distortion-ratio (SNDR) is improved from 40 to 66 dB and the spurious-free-dynamic-range (SFDR) is increased from 48 to 80 dB.

Keywords:
Background calibration
Pipelined analog to digital converters (ADCs)
Pseudorandom sequence

Published in: AEÜ-International Journal of Electronics and Communications (Volume 67, Issue 8, August  2013)

Publisher: Elsevier

ISSN Information: 1434-8411

A background calibration in pipelined ADCs

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