A novel hardware/software embedded system based on automatic censored target detection for radar systems

Authors: Ridha Djemal, Kais Belwafi, Walid Kaaniche, Saleh A. Alshebeili

Abstract:
This paper presents a practical design exploration for a new application related to real-time, highresolution target detection for radar systems. In this paper, an embedded architecture that combines the hardware and software components in a single platform is experienced using a field programmable gate array FPGA-based PC-board. The detection process utilises three techniques: namely, automatic censored ordered statistics detection (ACOSD), cell averaging (CA) and ordered statistics (OS) CFAR techniques, all of which operate in parallel to increase the accuracy of the detection and to reduce the false-alarm rate for both homogeneous and non-homogeneous environments. A prototype of the embedded system detector has been implemented for homogeneous and non-homogeneous environments on Stratix IV FPGA Board. The prototype operates at 200 MHz and performs real-time target detection with an execution delay of 0.27 s, which is less than the critical time (0.5 s) for high-resolution detection.

Keywords:
CFAR
FPGA
Radar
Embedded system
Co-design

Published in: AEÜ-International Journal of Electronics and Communications (Volume 67, Issue 4, April 2013)

Publisher: Elsevier

ISSN Information: 1434-8411

A novel hardware/software embedded system based on automatic censored target detection for radar systems

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