Window-constrained interconnect-efficient progressive edge growth LDPC codes

Authors: Aiman H. El-Maleh, Mohamed Adnan Landolsi, Esa A. AlGhoneim

Abstract:
One of the attractive features of low-density parity-check (LDPC) codes is the parallel iterative nature of their iterative belief propagation decoding, making them amenable to efficient hardware implementation. However, for an arbitrary code construction, the random-like connections between the code’s Tanner graph variable and check nodes makes fully-parallel implementation a difficult task as this leads to complex interconnect wiring androuting congestion.Inthispaper, wepresent anovel LDPCcodedesign approach, based on the progressive edge growth (PEG) Tanner graph construction, to solve the problem of dense connections between processing nodes. The approach is based on controlling the maximum connection length between processing nodes in order to make fully parallel implementation feasible. The proposed algorithm offers a good compromise between error correction performance and decoder complexity. Simulation results and FPGA-based implementation comparisons are presented to demonstrate the advantages of the proposed LDPC code constructions, and it is shown that, with proper windowconstrained node placement design, an improvement of up to 40% in interconnect efficiency is achievable without any significant degradation in error correction capability.

Keywords:
LDPC codes
Progressive edge growth
Interconnect complexity
Routing congestion

Published in: AEÜ-International Journal of Electronics and Communications (Volume 67, Issue 7, July  2013)

Publisher: Elsevier

ISSN Information: 1434-8411

Window-constrained interconnect-efficient progressive edge growth LDPC codes

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